1. Technical Field
The present disclosure relates generally to interconnect structures formed in semiconductor devices. In particular, the present disclosure relates to a structure and methods of forming metal interconnect structures in porous ultra low-k dielectric.
2. Description of Related Art
Integrated circuit chips typically include two or more levels of conductive lines which are vertically spaced apart and separated by intermediate insulating layers. Interconnections are formed between the levels of conductive lines in the chip for providing high wiring density and good thermal performance. The interconnections are formed by means of lines and vias which are etched through the insulating layers separating the levels. The lines and vias are then filled with a conductive material or metal (e.g. Copper) to form interconnect elements (i.e. via studs).
One preferred method of making interconnect wiring networks is the damascene process. A typical damascene process for producing a multilevel structure would include: a blanket deposition of a dielectric material; pattering of the dielectric material to form openings; deposition of a conductive material onto the substrate in sufficient thickness to fill the openings; and removal of excessive conductive material from the substrate surface using a chemical reactant-based process, mechanical methods, or combined chemical-mechanical polishing techniques. A typical interconnect element includes metal vias running perpendicular to the semiconductor substrate and metal lines running parallel to the semiconductor substrate. This process results in multiple levels of conductor wiring interconnection patterns, having individual levels connected by via studs and operating to distribute signals among the various circuits on the chip. Traditionally, the dielectric material is made from an inorganic glass like silicon dioxide (SiO2) or a fluorinated silica glass (FSG) film deposited by plasma enhanced chemical vapor deposition (PECVD).
A dual damascene (DD) process is another well known method of making interconnect wiring networks. In the standard DD process, the wiring interconnect network consists of two types of features: line features that traverse a certain distance across the chip, and via features which connect together lines in different levels of interconnects in a multilevel stack. Because two interconnect features are simultaneously defined to form a conductor inlaid within an insulator by a single polish step, this process is referred to as dual damascene process.
With the progress in the transistor device technology leading to the present ultra large scale integration, the overall speed of operation of these advanced chips are beginning to be limited by the signal propagation delay in the interconnection wires between the individual devices on the chips. The signal propagation delay in the interconnect structures is dependent on the resistance of the interconnect wires and the overall capacitance of the interconnect scheme in which the wires are embedded. The current focus in the microelectronics industry in building the multilayered interconnect structures on chips, is to reduce the capacitance by the use of lower dielectric constant (k) insulators, by introducing porosity in these insulators. However, the reliability of metal interconnects in porous ultra low-k dielectrics is a critical concern. In particular, the electromigration lifetime of wide-line interconnects is poor due to a lack of a liner contact between the landing via and the liner in the underlying line. Since the porous dielectric is prone to severe erosion during etch-back step needed for via embedment within the underlying line, localized “fangs” or deep and sharp trenches are formed at the bottom of the line. Because of the severe topography, these fangs are not appropriately covered with the liner. As a result, in view of a voltage bias, the metal can readily leak out through the exposed area causing time-dependent dielectric breakdown (TDDB) leakage failure as well as time-zero leakage. At present, there are no known solutions to this problem.
Accordingly, a novel method of interconnect fabrication is proposed for making a reliable metal interconnect in porous ultra low-k dielectric that would address the aforementioned challenges.